// not use 


module branchPC(
    input [31:0] extImm,
    input [31:0] PC,
    input [31:0] target,
    input branchOp     ,
    output reg [31:0] branchPC 
);
    always @(*) begin
        if (branchOp == 1'b0)   
            branchPC = target;
        else 
            branchPC = PC+{extImm[29:0],2'b00};
    end
endmodule // branchPC